Videos
Demo: AI-Based Timing Sync on Altera® Agilex™ 7 SoC FPGAs | AI-Powered RAN Sync During GNSS Holdover
Altera
Can your network maintain timing when GNSS fails?
From the Mobile World Congress show floor, see how Altera is redefining synchronization in RAN and embedded systems with an AI-powered timing holdover solution.
In this demo, you’ll see how MLP and LSTM models are deployed on Altera® Agilex™ 7 SoC FPGAs, using the FPGA AI Suite, to intelligently predict clock drift and keep networks synchronized during holdover situations like GNSS/GPS outages. This approach dramatically reduces power consumption (up to 10x) and lowers costs (up to 10x) compared to traditional holdover implementations.
🔗IP web page: https://www.intel.com/content/www/us/...
🔗 White paper: https://www.intel.com/content/www/us/...
Related
-
Creating Reusable Design Blocks: IP Design & Implementation with the Intel® Quartus® Prime Software
- Altera
- Intellectual property
-
OpenCL™ Coding Optimizations for Intel® Stratix® 10 Devices
- Altera
- Company / Market Trends
-
Building RTL Workloads for the Acceleration Stack for Intel® Xeon® CPU with FPGAs
- Altera
- Microcontrollers
-
The Realtime Group - Intel FPGA Solutions Powered by Realtime
- Altera
- Company / Market Trends
-
IntelliProp - NVMe to SATA Bridge IP Core
- Altera
- Company / Market Trends
-
Design Gateway - NVMe IP core on Intel Arria 10 SX with Intel Optane SSD 900P
- Altera
- Network/Telecommunication
-
Design Gateway - TOE10G IP core on Intel Arria 10 SX
- Altera
- Network/Telecommunication
-
Accelize - Solutions to boost Cloud and Enterprise workloads with Intel FPGAs
- Altera
- Network/Telecommunication
-
S2C - FPGA Prototyping Services
- Altera
- Logic/PLD
-
eInfochips - Introducing eInfochips FPGA design services
- Altera
- Network/Telecommunication
-
Alorium Technology - Intel MAX 10 FPGA Platforms
- Altera
- Company / Market Trends
-
Vadatech - Intel FPGA solutions are VadaTech
- Altera
- Company / Market Trends
-
PLDA - PCIe IP Experts
- Altera
- Network/Telecommunication
-
OpenCL™ Development with the Acceleration Stack for Intel® Xeon® CPU with FPGA
- Altera
- Microcontrollers
-
Booting Linux in Intel® Stratix® 10 SoC FPGA
- Altera
- Company / Market Trends
-
SEU Mitigation in Intel® FPGA Devices: Fault Injection
- Altera
- Logic/PLD
-
Running OpenCL™ on Intel® FPGAs
- Altera
- Company / Market Trends
-
Introduction to Intel® FPGAs for Software Developers
- Altera
- Processor/Memory
-
Intel® Stratix® 10 SoC FPGA Technical Overview
- Altera
- Processor/Memory
-
Introduction to OpenCL™ on FPGAs for Parallel Programmers
- Altera
- Processor/Memory
