| 2025/01/16 |
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PCN(Product Change Notice)
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Description of change Old:Before setting the system clock (SYSCLK) frequency to 48 MHz, the flash memory latency must be set to one wait state. However, the code generated by STM32CubeMX (versions before v6.13.0), and the project examples available in the STM32CubeC0 software packages (versions before v1.3.0), do not ensure this.
New: The fix consists in setting the number of wait states to one, before setting the HSI48 clock division factor to one. This fix is implemented in the following (andany subsequent) versions: - STM32CubeC0 v1.3.0 (November 2024) - STM32CubeMX v6.13.0 (November 2024) See more details in Additional Information document attached to this PCI |
| 2025/01/16 |
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PCN(Product Change Notice)
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Supplier Notice No.:MICROCONTROLLERS/25/15132 Title: Enhancement of STM32C011x, STM32C031x & STM32C071x HAL settings when using internal clock at 48MHz (STM32CubeMX and STM32CubeC0)
Description of change: Old:Before setting the system clock (SYSCLK) frequency to 48 MHz, the flash memory latency must be set to one wait state. However, the code generated by STM32CubeMX (versions before v6.13.0), and the project examples available in the STM32CubeC0 software packages (versions before v1.3.0), do not ensure this.
New: The fix consists in setting the number of wait states to one, before setting the HSI48 clock division factor to one. This fix is implemented in the following (andany subsequent) versions: - STM32CubeC0 v1.3.0 (November 2024) - STM32CubeMX v6.13.0 (November 2024) See more details in Additional Information document attached to this PCI
Intended start of delivery: 2024-11-03 |
| 2025/07/18 |
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PCN(Product Change Notice)
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PCN No. CRP/25/15294 Change Desc. Additional 2D in ST Standard Inner Bulk Label (MDRF perimeter)
Timing / schedule Intended start of delivery 2025-08-18 |