Videos
Verifying Memory Interfaces in Intel® Agilex™ Devices
Intel
This training is part 3 of 4. Intel® Agilex™ devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 3.2 Gbps on some devices. This part of the training discusses how to perform a simulation of the altera_emif_fm IP using a generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for altera_emif_fm along with easier-to-read timing reports simplify analysis and closure.
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