Videos
On-Chip Debugging of Memory Interfaces in Intel® Agilex™ Devices
Intel
This training is part 4 of 4. Intel® Agilex devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 3.2 Gbps on some devices. This part of the training discusses the use of the EMIF Debug Toolkit and the new Traffic Generator 2.0. The Debug Toolkit provides runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. The Traffic Generator lets you create and send custom data patterns to the memory for post-calibration tests. Due to the changes in implementation from previous devices, this training also discusses what is required to use these tools with designs that include multiple memory interfaces.
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