53. Types and features of Semi-custom programmable logic IC’s
The technique to acquire the semiconductor chip equipped with the function desired by the electronic equipment manufacturer can be largely classified into four. The first one is the method to design the custom chip. If this method is used, you can obtain a chip equipped with function which is exactly same as desired, however the development cost rises considerably besides the development period becomes longer. The second method is buying ready-made goods (ASSP). If the chip equipped with the desired function is available in the market, then the cost will be greatly decreased. However, such chip doesn’t necessarily exist in the market. Then, the following two techniques are very popular now. It is a technique that uses a semi-custom chip such as ASIC, and a technique that uses the programmable device named FPGA/CPLD. However, there are various types of semi-custom/programmable device and it is necessary to use properly according to the usage (application). The following explains the feature of various semi-customs/programmable devices.
Types of IC | Characteristic |
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Gate Array |
This is a semi-custom device where only the separate wiring layer is created for each user and the basic logic device is laid on the chip in advance. There is an advantage for shorter development because LSI will be completed only by design / manufacturing the wiring layer. Further, the cost can be bought down because the master chip laid only in the gate can be manufactured in large amount. However, on the other hand, there is a disadvantage that the components per chip and the processing performance are comparatively low to compose the circuit by the combination of the standard gates. ![]() |
Cell Based |
It is the product deployed with designed completed functional circuit block, created with wiring layer between these intervals except the circuit. The components per chip and the performance are excellent when compared to Gate Array, but inferior in manufacturing period and the production cost. ![]() |
Embedded Array |
It is a semi-custom device where designed completed functional block is embedded in a portion on the foundation of Gate Array, and the remaining logic will be wired by using the Gate Array. It can be called the combination type of Gate Array and Cell Based. |
Standard Cell |
In general, it is used as pseudonym of ASIC of Cell Based Type. However, there are cases of using as generically of three types that is Gate Array, Cell base, and Embedded Array according to the semiconductor manufacturer. |
Structured ASIC |
The semiconductor manufacturer is preparing multiple types of master chips that accumulated the functional block necessary in each usage, the user will choose the suitable master chip among these, so it is the semi- custom device that can obtain the desired function by designing only the wiring layer. There is an advantage that the development period and the cost of the mask set are suppressed compared to Gate Array and Cell Based when seen from the user side. However, there is a major disadvantage to the semiconductor manufacturer side because they have to arrange various types of master chip when dealing with many users. |
FPGA |
It is a programmable logic device which used small scale basic logic cell. The input output section of each basic logic cell is connected with the wiring layer, and can achieve arbitrary function by designing (program) the connection status of the wiring layer by the user. The design information (program data) is stored in SRAM or in flash memory, and the operation starts simultaneously when the power is on for the device and information (data) is downloaded. There is an advantage with lot of flexibility for the design. However, on the other hand, there is a disadvantage that the performance of the designed device (processing speed, gate use efficiency) largely depends on the ability of the design tool and the designer. ![]() |
CPLD |
It is a programmable logic device which uses a comparatively large basic logic cell. There is an advantage with a less variation of the performance by the difference of the ability of the designer and the development tool however there is less flexibility for the design compared to FPGA. ![]() |